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Japan; specific worksite, salary, employment terms, start date and relocation/visa support must be confirmed for the assignment.
SystemVerilog · UVM · Functional coverage · Fault injection
Responsibilities
- Build and run module/full-chip verification with SystemVerilog and UVM.
- Manage simulation, regression and coverage closure, including fault-injection verification.
Requirements
- SystemVerilog and UVM verification skills are required.
- Preferred: automotive chip verification experience.
- Bachelor’s degree in semiconductors, electronics or a related field.
- Working proficiency in English OR Japanese; both are not required by this brief.
- Relevant hands-on experience and willingness to work on-site in Japan long term.