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Japan; specific worksite, salary, employment terms, start date and relocation/visa support must be confirmed for the assignment.
MCU · Verilog · RTL · Synthesis · Timing closure
Responsibilities
- Develop Verilog RTL for MCU cores and peripherals.
- Perform synthesis, timing closure and design reviews with safety and reliability considerations.
Requirements
- MCU architecture and peripheral design experience.
- Verilog RTL design skills; automotive chip experience is preferred.
- Bachelor’s degree in semiconductors, electronics or a related field.
- Working proficiency in English OR Japanese; both are not required by this brief.
- Relevant hands-on experience and willingness to work on-site in Japan long term.